The present invention relates to a data processor such as a microprocessor or a microcomputer and, more particularly, to a wait state control unit in a data processor for controlling the insertion of one or more wait states into a sequence of states for performing each bus cycle.
A data processor constitutes an information processing system together with a memory unit and a plurality of peripheral I/O (Input/Output) units. When the data processor reads or writes data from or into the memory units and the peripheral I/O units, it performs a data read or a data write bus cycle in accordance with a sequence of states, the number of which is determined by a bus control unit of the data processor and consists of a few states in general. Each of the states corresponds to one cycle period of a system clock signal.
As well known in the art, an information processing system does not always employ memory devices constituting the memory unit and the peripheral I/O units each having a high speed access time. One or more memory devices and/or one or more peripheral I/O units having a low speed access time may be employed. In such a case, necessary data may not be read or written from or into the memory device and the I/O unit within an access time determined by the bus cycle of the bus control unit.
In order to overcome this shortcoming, a wait state control unit is provided in the data processor for controlling or prolonging the bus cycle of the data processor. This unit generates a ready signal in response to a bus cycle to be performed to inform the bus control unit of the unit currently accessed having the low speed access time. As long as the ready signal is generated, the bus control unit inserts a wait state into the sequence of states for performing the bus cycle. The wait state control unit includes a bus cycle judgement circuit for judging the kind of bus cycles to be currently performed, a register for storing a plurality of wait cycle numbers to be inserted, a wait cycle selector and decoder for selecting one of the wait cycle numbers in response to the judged kind of the bus cycle and decoding the selected wait cycle number, and a ready signal generator for responding to the decoded bus cycle number to generate the ready signal until the wait state is inserted in the bus cycle by a number designated by the decoded wait cycle number.
Recently, the data processor has been required to operate at a high speed. For this purpose, the frequency of the system clock signal is made high and the bus control unit performs each of the data read and data write bus cycles by two states. In this case, the bus control unit samples the ready signal from the wait state control unit at an intermediate time point during the second state to determine whether or not the wait state is to be inserted. This means that the wait state control unit must generate the ready signal within a time corresponding to one and a half clock cycles of the system clock signal.
However, the wait state control unit according to the prior art performs the operation thereof in a sequential manner, as described above. In other words, the wait state control unit requires a relatively long operation time for generating the ready signal. For this reason, the enhancement in the operation speed of the data processor is restricted.